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sv1hw.h.z
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sv1hw.h
Wrap
C/C++ Source or Header
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1992-04-03
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15KB
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609 lines
/*
* $Revision: 1.3 $
*/
#ifndef __SV1_HW_H_
#define __SV1_HW_H_
#define LOW_7(X) (X & 0x7f)
#define LOW_8(X) (X & 0xff)
#define LOW_10(X) (X & 0x3ff)
#define GIO_BUS_DELAY 15
#define SEND_PIXKEY_RAM(I,X) {*((long *)(PIX_VIRT_ADDR)+I) = X;}
#define DENC_CLUT_LEN 256
#define SEND_DENC_CTRL(D,I,X) {D->dencAdrCtl = I; D->dencDatCtl = X;}
#define SEND_DENC_CTRL_ARRAY(D,I,X) \
{int i; \
D->dencAdrCtl = I; \
for (i = 0; X[i] != 0xffffffff; i++) { \
D->dencDatCtl = X[i]; \
} }
#ifndef KTRACE
#define TRACE0(T,S)
#define TRACE1(T,S,A)
#define TRACE2(T,S,A,B)
#define TRACE3(T,S,A,B,C)
#endif /* KTRACE */
/*
* This is a software flag to indicate whether or not we
* want to disable the hardware. It does not make any
* state change in the hardware.
*/
#define HARDWARE_DISABLE(X) {hardware_state = X;}
/*
* Pixkey count.
*/
#define PIXKEY_COUNT 0x100
/*
* Status return values.
*/
#define STATUS_OK 0x00
#define STATUS_ERR -1
#define STATUS_I2C_TIMEOUT 0x01
/*
* Base addresses of the various sections of the 64k SV1
* address space.
*/
#define SVB_PHYS_ADDR 0x1f3e0000
#define DENC_PHYS_ADDR (SVB_PHYS_ADDR + 0x800)
#define PIX_PHYS_ADDR (SVB_PHYS_ADDR + 0xc00)
#define CLI_PHYS_ADDR (SVB_PHYS_ADDR + 0x1000)
#define SRTV_PHYS_ADDR (SVB_PHYS_ADDR + 0x2000)
#define SVB_MAX_ADDR 0x10000
#define SVB_VIRT_ADDR (PHYS_TO_K1(SVB_PHYS_ADDR))
#define DENC_VIRT_ADDR (PHYS_TO_K1(DENC_PHYS_ADDR))
#define PIX_VIRT_ADDR (PHYS_TO_K1(PIX_PHYS_ADDR))
#define CLI_VIRT_ADDR (PHYS_TO_K1(CLI_PHYS_ADDR))
#define SRTV_VIRT_ADDR (PHYS_TO_K1(SRTV_PHYS_ADDR))
#define CHECK_SV(S) if (S != (SVR_Regs *)SVB_VIRT_ADDR) printf ("bad sv 0x%x\n", S);
#define CHECK_DENC(D) if (D != (DENC_Regs *)DENC_VIRT_ADDR) printf ("bad denc 0x%x\n", D);
/*
* SVB CLUT offsets
*/
#define SVBLUT00 0x00
#define SVBLUT01 0x01
#define SVBLUT02 0x02
#define SVBLUT03 0x03
#define SVBLUT_INC 0x04
/*
* LUT data types
*/
#define MONO_LUT 0x00
#define RGB332V1_LUT 0x01
#define RGB332GLRGB_LUT 0x02
/*
* BT479 definitions
*/
#define BTPAL00 0x00
#define BTPAL01 0x10
#define BTPAL02 0x20
#define BTPAL03 0x30
/*
* Pointer Data for registers (serial i/o is off)
*/
#define SV_I2C_OWNADDR_REG 0x00
#define SV_I2C_CLK_REG 0x20
/*
* Pointer Data for registers (serial i/o is on)
*/
#define SV_I2C_SLV_ADDR_REG 0x40 /* set address */
#define SV_I2C_SUB_ADDR_REG 0x45 /* set subaddress */
#define SV_I2C_STOP 0xc3 /* set STOP */
/*
* 8584 I2C Controller self address.
*/
#define SV_I2C_8584_ADDR 0x55
/*
* Init Data.
*/
#define SV_I2C_CLK_8MHZ 0x18
/*
* Status Masks.
*/
#define SV_I2C_SERIAL_BUSY 0x80
/*
* Delay and timeout for I2C serial transfers. We wait
* SV_I2C_TIMEOUT_DELAY reps on each timeout cycle, and for
* SV_I2C_TIMEOUT timeouts in total.
*/
#define SV_I2C_TIMEOUT 0x1000
#define SV_I2C_TIMEOUT_DELAY 0x08
#define SV_I2C_TIMEOUT_REPEAT 0x10 /* how often clients of I2C
should attempt transfer. */
/*
* Broadcast standards.
*/
#define NTSC 0
#define PAL 1
/*
* Video rate.
*/
#define RATE_60HZ 0
#define RATE_50HZ 1
/*
* FUNC_CTL_REG
*/
#define SV_COLOR_SET 0x80
#define SV_MONO_SET 0x7F
#define SV_NTSC_SET 0xEF
#define SV_PAL_SET 0x10
#define SV_BYPASS_VLUT_SET 0xBF
#define SV_USE_VLUT_SET 0x40
#define SV_FRAMEGRAB_SET 0x20
#define SV_FRAMEGRAB_OFF 0xDF
#define SV_FIELD_DROP_SET 0xF7
#define SV_FIELD_DROP_OFF 0x08
#define SV_DITHER_SET 0xFB
#define SV_DITHER_OFF 0x04
#define SV_FILTER_SET 0xFD
#define SV_FILTER_OFF 0x02
#define SV_SLAVEOI_SET 0x01
#define SV_SLAVEOI_OFF 0xFE
#define SVB_24YUV_DMA_SETUP 0x08 /* dma YUV fifo1 -> GIO */
#define SVB_24YUV_DMA_SETUP1 0xcc /* dma YUV fifo1 -> GIO */
#define SVB_24YUV_DMA_SETUP2 0xc8 /* dma YUV fifo1 -> GIO */
#define SVB_24YUV4_DMA_SETUP1 0xec /* dma YUV quarter fifo1 -> GIO */
#define SVB_24YUV4_DMA_SETUP2 0xe8 /* dma YUV quarter fifo1 -> GIO */
#define SVB_INIT_DMA_SETUP 0xC0 /* init val */
#define SVB_INIT_CLOCK_SETUP 0x00 /* init val XXX was 0x04 */
#define SVB_24YUV_CLOCK_SETUP2 0x24 /* yuv run val */
#define SVB_24YUV_CLOCK_SETUP1 0xA4 /* yuv init val */
#define SVB_24YUV_BUS_SETUP 0x6A /* fifo1 -> GIO */
#define SVB_INIT_BUS_SETUP 0x7A /* vid -> screen, screen -> out */
#define SVB_VOUT_BUS_SETUP 0xEA /* vc1 -> video */
/*
* CSC addresses and subaddresses.
*/
#define CSC_ADDR 0xE0
#define CSC_CONTROL_REG 0x00
#define CSC_LUT_REG 0x01
#define CSC_WRITE_LUTS 0xBF
#define CSC_READ_LUTS 0x40
#define CSC_MONO_VLUT_LD 0x34
#define CSC_MONO_VLUT_RUN 0x74
#define CSC_COLOR8_VLUT_LD 0x38
#define CSC_COLOR8_VLUT_RUN 0x78
#define CSC_COLOR9_VLUT_LD 0x39
#define CSC_COLOR9_VLUT_RUN 0x79
#define CSCA_RLUT_REG 0x01
#define CSCA_GLUT_REG 0x02
#define CSCA_BLUT_REG 0x03
#define CSCA_LUTS_REG 0x04
/*
* DMSD
*/
#define DMSD_ADDR 0x8A
#define DMSD_PAGE1 0x00
#define DMSD_PAGE2 0x14
/*
* DMSD subaddresses.
*/
#define DMSD_REG_IDEL 0x00
#define DMSD_REG_HSYB50 0x01
#define DMSD_REG_HSYE50 0x02
#define DMSD_REG_HCLB50 0x03
#define DMSD_REG_HCLE50 0x04
#define DMSD_REG_HSP50 0x05
#define DMSD_REG_LUMA 0x06
#define DMSD_REG_HUE 0x07
#define DMSD_REG_CKQAM 0x08
#define DMSD_REG_CKSECAM 0x09
#define DMSD_REG_SENPAL 0x0A
#define DMSD_REG_SENSECAM 0x0B
#define DMSD_REG_GC0 0x0C
#define DMSD_REG_STDMODE 0x0D
#define DMSD_REG_IOCLK 0x0E
#define DMSD_REG_CTRL3 0x0F
#define DMSD_REG_CTRL4 0x10
#define DMSD_REG_CHCV 0x11
#define DMSD_REG_HSYB60 0x14
#define DMSD_REG_HSYE60 0x15
#define DMSD_REG_HCLB60 0x16
#define DMSD_REG_HCLE60 0x17
#define DMSD_REG_HSP60 0x18
#define DMSD_CHCV_NTSC 0x2C
#define DMSD_CHCV_PAL 0x59
/* theDMSD.dmsdRegLUMA */
#define DMSD_PREF_SEL_ON 0x40
#define DMSD_PREF_SEL_OFF 0xFFFFFFBF
#define DMSD_CTBS_SEL_ON 0x80
#define DMSD_CTBS_SEL_OFF 0xFFFFFF7F
#define DMSD_APER_MASK 0xFFFFFFFC
#define DMSD_APER_BITS 0x03
#define DMSD_CORI_MASK 0xFFFFFFF3
#define DMSD_CORI_BITS 0x0C
#define DMSD_BPSS_MASK 0xFFFFFFCF
#define DMSD_BPSS_BITS 0x30
/* theDMSD.dmsdRegSTDmode */
#define DMSD_TV_MODE_SEL 0xFFFFFF7F
#define DMSD_VTR_MODE_SEL 0x80
/* theDMSD.dmsdRegIOclk */
#define DMSD_INPUT_SEL_MASK 0xFFFFFFFC
#define DMSD_INPUT_SEL_0 0x00
#define DMSD_INPUT_SEL_1 0x01
#define DMSD_INPUT_SEL_2 0x02
#define DMSD_COMP_MODE_SEL 0xFFFFFFFB
#define DMSD_SVID_MODE_SEL 0x04
#define DMSD_HPLL_SEL_ON 0xFFFFFF7F
#define DMSD_HPLL_SEL_OFF 0x80
/*
* DMSD.dmsdRegGC0.
*/
#define DMSD_COL_SEL_ON 0x80
#define DMSD_COL_SEL_OFF 0xFFFFFF7F
#define DMSD_LFIS_MASK 0xFFFFFF9F
#define DMSD_LFIS_BITS 0x60
/*
* DMSD.dmsdRegCTRL3.
*/
#define DMSD_YDEL_MASK 0xFFFFFFF8
#define DMSD_YDEL_BITS 0x07
#define DMSD_OFTS_SEL411_ON 0xFFFFFFF7
#define DMSD_OFTS_SEL422_ON 0x08
#define DMSD_AUFD_SEL_ON 0x80
#define DMSD_AUFD_SEL_OFF 0xFFFFFF7F
/*
* DMSD.dmsdRegCTRL4.
*/
#define DMSD_VNOI_MASK 0xFFFFFFFC
#define DMSD_VNOI_BITS 0x03
#define DMSD_HRFS_SEL_PHIL 0xFFFFFFFB
#define DMSD_HRFS_SEL_CCIR 0x04
/*
* H functions.
*/
enum H_function {NO_H_FUNCTION = 0, HSYb, HSYe, HCLb, HCLe, HSps,
HUE, CKQAM, CHCV, IDEL, APERTURE_FACT, CORING,
APERTURE_BAND, AGC_LOOP, YDEL, VNOI,
HPLL_FUNC, PREF_FUNC, CTBS_FUNC, COMP_FUNC, COLS_FUNC,
OFTS_FUNC, AUFS_FUNC, HRFS_FUNC};
enum color_flags {COLOR_NONE = 0,COLOR_0, COLOR_8, COLOR_9};
/*
* DMSD.dmsdRegCTRL3
*/
#define DMSD_FSEL_SEL50_ON 0xFFFFFFBF
#define DMSD_FSEL_SEL60_ON 0x40
/*
* DENC internal register indices.
*/
#define DENC_REG_IN00 0x00
#define DENC_REG_IN01 0x01
#define DENC_REG_IN02 0x02
#define DENC_REG_IN03 0x03
#define DENC_REG_SYNC00 0x04
#define DENC_REG_SYNC01 0x05
#define DENC_REG_SYNC02 0x06
#define DENC_REG_SYNC03 0x07
#define DENC_REG_OUT00 0x08
#define DENC_REG_OUT01 0x09
#define DENC_REG_OUT02 0x0A
#define DENC_REG_OUT03 0x0B
#define DENC_REG_ENCODE00 0x0C
#define DENC_REG_ENCODE01 0x0D
#define DENC_REG_ENCODE02 0x0E
#define VIDEO_MAP_SIZE 256
/* MOD 0-1 - (0,1) */
#define DENC_MOD_MASK 0xFC
#define DENC_GENLOCK_ON 0x00
#define DENC_STANDALONE_ON 0x01
#define DENC_MASTER_ON 0x02
#define DENC_TEST_ON 0x03
/* VTBY - (7) */
#define DENC_VTBY_MASK 0x7F
#define DENC_VTBY_ON 0x00
#define DENC_VTBY_OFF 0x80
/* SRC - (5) */
#define DENC_SRC_MASK 0xDF
#define DENC_SRC_EXT_ON 0x00
#define DENC_SRC_DTV2_ON 0x20
/*
* Initial values.
*/
#define INIT_VS0_IDEL 0x51
#define INIT_VS1_HSYb50 0x30
#define INIT_VS2_HSYe50 0x00
#define INIT_VS3_HCLb50 0xE8
#define INIT_VS4_HCLe50 0xB6
#define INIT_VS5_HSps50 0xF4
#define INIT_VS6_HUE 0x00
#define INIT_VS7_CKQAM 0xF8
#define INIT_VS8_CHCV 0x2C
#define INIT_VS1_HSYb60 0x31
#define INIT_VS2_HSYe60 0x0A
#define INIT_VS3_HCLb60 0xF4
#define INIT_VS4_HCLe60 0xCE
#define INIT_VS5_HSps60 0x0A
#define INIT_VS9_APER 0x01 /* 0x06 LUMA */
#define INIT_VS10_CORI 0x00 /* 0x06 LUMA */
#define INIT_VS11_BPSS 0x00 /* 0x06 LUMA */
#define INIT_VS12_LFIS 0x00 /* 0x0C GC0 */
#define INIT_VS13_YDEL 0x01 /* 0x0F CTRL #3 */
#define INIT_VS14_VNOI 0x00 /* 0x10 CTRL #4 */
/*
* Structures to describe the hardware:
*
* DMSD Register struct.
*/
typedef struct dmsd_regs {
long dmsdRegIDEL; /* 0x00 - 0x50 */
long dmsdRegHSYb50; /* 0x01 - 0x30 */
long dmsdRegHSYe50; /* 0x02 - 0x00 */
long dmsdRegHCLb50; /* 0x03 - 0xE8 */
long dmsdRegHCLe50; /* 0x04 - 0xB6 */
long dmsdRegHSP50; /* 0x05 - 0xF4 */
long dmsdRegLUMA; /* 0x06 - 0x01 */
long dmsdRegHUE; /* 0x07 - 0x00 */
long dmsdRegCKqam; /* 0x08 - 0xF8 */
long dmsdRegCKsecam; /* 0x09 - 0xF8 */
long dmsdRegSENpal; /* 0x0A - 0x90 */
long dmsdRegSENsecam; /* 0x0B - 0x90 */
long dmsdRegGC0; /* 0x0C - 0x00 */
long dmsdRegSTDmode; /* 0x0D - 0x00 */
long dmsdRegIOclk; /* 0x0E - 0x79 */
long dmsdRegCTRL3; /* 0x0F - 0x91 (0xD1) */
long dmsdRegCTRL4; /* 0x10 - 0x00 */
long dmsdRegCHCV; /* 0x11 - 0x2C */
long dmsdTerminate1; /* XXXX - 0xFFFF */
long dmsdRegHSYb60; /* 0x14 - 0x34 */
long dmsdRegHSYe60; /* 0x15 - 0x0A */
long dmsdRegHCLb60; /* 0x16 - 0xF4 */
long dmsdRegHCLe60; /* 0x17 - 0xCE */
long dmsdRegHSP60; /* 0x18 - 0xF4 (0x0A) */
long dmsdTerminate2; /* XXXX - 0xFFFF */
long videoRate; /* XXXX */
long videoStandard; /* XXXX */
} DMSD_Regs;
typedef struct denc_struct {
long dencRegIn00; /* 0x00 - 0xA0 - 0xA1 */
long dencRegIn01; /* 0x01 - 0x00 - 0x00 */
long dencRegIn02; /* 0x02 - 0x00 - 0x00 */
long dencRegIn03; /* 0x03 - 0x00 - 0x00 */
long dencRegSync00; /* 0x04 - 0xF0 - 0xF0 */
long dencRegSync01; /* 0x05 - 0x00 - 0x00 */
long dencRegSync02; /* 0x06 - 0x52 - 0x52 */
long dencRegSync03; /* 0x07 - 0x00 - 0x00 */
long dencRegOut00; /* 0x08 - 0x60 - 0x40 */
long dencRegOut01; /* 0x09 - 0x00 - 0x00 */
long dencRegOut02; /* 0x0A - 0x00 - 0x00 */
long dencRegOut03; /* 0x0B - 0x00 - 0x00 */
long dencRegEncode00; /* 0x0C - 0x00 - 0x00 */
long dencRegEncode01; /* 0x0D - 0x00 - 0x00 */
long dencRegEncode02; /* 0x0E - 0x0C - 0x0C */
long dencTerm;
} DencStruct;
/*
* Local Data bus, Board Rev, I2C, DENC, Pixkey Registers.
*/
typedef struct denc_regs {
long BoardRevId; /* 0x800 */
long I2cCsCtl; /* 0x804 */
long I2CCsData; /* 0x808 */
long dencUnused1; /* 0x80c */
long dencAdrClut; /* 0x810 */
long dencDatClut; /* 0x814 */
long dencAdrCtl; /* 0x818 */
long dencDatCtl; /* 0x81c */
} DENC_Regs;
/*
* SVR Registers
*/
typedef struct SVR_regs {
long svrRevId; /* 0x00 */
long svrConfCtl; /* 0x04 */
long svrDmaCtl; /* 0x08 */
long svrDmaData; /* 0x0c */
long svrInXStart; /* 0x10 */
long svrInXEnd; /* 0x14 */
long svrInYStart; /* 0x18 */
long svrInYEnd; /* 0x1c */
long svrDecimation; /* 0x20 */
long svrOutXStart; /* 0x24 */
long svrOutYStart; /* 0x28 */
long svrBusCtl; /* 0x2c */
long svrFuncCtl; /* 0x30 */
long svrClockMode; /* 0x34 */
} SVR_Regs;
typedef struct videochip {
SVR_Regs sv_regs;
} VideoChip;
extern int gio_bus_delay;
#define REGS_FROM_GFX(G,S,D) \
{ \
struct video_board *gfxb; \
struct video_info *info; \
struct VideoDevice *board; \
\
if (!(gfxb = G->vx_board)) { \
printf ("gfxb 0x%x\n", gfxb); \
return (-1); \
} \
if (!(info = (struct video_info *)(gfxb->vb_info))) { \
printf ("info 0x%x\n", info); \
return (-1); \
} \
if (!(board = info->video_board)) { \
printf ("board 0x%x\n", board); \
return (-1); \
} \
if (board->info != info) { \
printf ("board->info 0x%x info 0x%x\n", \
board->info, info); \
return (-1); \
} \
S = board->sv_regs; \
D = board->denc; \
}
struct aCSC {
long theModeReg;
};
extern DencStruct aDENC;
extern unsigned char clutDENCdataRed[];
extern unsigned char clutDENCdataGreen[];
extern unsigned char clutDENCdataBlue[];
extern long cscLUTData1[];
extern long csclut_rg[];
extern long csclut_b[];
struct param_values {
int current;
int lowest;
int highest;
int call_param;
int (*call_func)();
};
extern struct param_values ParamValues[];
struct low_param_values_calls {
int (*sv_call_func)();
int (*denc_call_func)();
};
extern struct low_param_values_calls LowParamValuesCalls[];
struct init_general {
int (*sv_call_func)();
int sv_value;
int (*denc_call_func)();
int denc_flag;
int denc_value;
};
extern struct init_general Init_General[];
extern int sv1_edtinit_called;
struct init_values {
enum boolean InitHPLL;
enum boolean InitPFLT;
enum boolean InitCTBS;
enum boolean InitCOL;
enum boolean InitOFTS;
enum boolean InitAUFD;
enum boolean InitHRFS;
enum bypass_value InitVLUT;
enum framegrab_value InitGRAB;
enum fielddrop_value InitTEAR;
enum dither_value InitDITH;
enum filter_value InitFILT;
enum slave_value InitSLAVEOI;
int InitISEL;
enum input_type InitITYP;
enum video_mode InitIVSYS;
enum broadcast_std InitIVSTD;
enum video_rate Init5060;
enum color_value InitCOMO;
long InitIDEL;
int InitHSYb;
int InitHSYe;
int InitHCLb;
int InitHCLe;
int InitHSps;
long InitHUE;
long InitCK;
long InitCHCV;
int InitAPER;
int InitCORI;
int InitBPSS;
int InitLFIS;
int InitYDEL;
int InitVNOI;
enum boolean InitCLUT;
enum boolean InitSA;
};
struct video_coords {
int x_start;
int x_end;
int y_start;
int y_end;
int decimation;
int Source;
};
#endif /* __SV1_HW_H_ */